About the Role
We are seeking a Senior Analog IC Layout Engineer to implement high-quality analog and mixed-signal layouts and contribute to full-chip physical integration of our CapRAM-based AI hardware. You will work closely with circuit designers and other engineering teams, taking ownership of layout implementation, physical verification, and chip-level integration through tape-out.Location: Dresden, Germany (On-site)
What you will do:
- Implement and optimize precision analog and mixed-signal layouts, applying advanced matching techniques such as interdigitation, common-centroid placement, symmetry, shielding, and guard rings.
- Perform full-chip integration, including block placement, I/O ring implementation, power distribution networks, and global/local signal routing using routing conduits and structured routing methodologies.
- Optimize layouts for matching, parasitic effects, noise isolation, signal integrity, and power distribution.
- Perform physical verification, including Design Rule Checking (DRC), Layout Versus Schematic (LVS), Electrical Rule Checking (ERC), electromigration (EM), and IR-drop analysis, and resolve identified violations.
- Collaborate with analog and digital design engineers on floorplanning, layout constraints, and integration requirements.
- Support parasitic extraction, post-layout verification, and final layout sign-off for tape-out.
What you should bring in:
- Bachelor's degree in Electrical Engineering, Microelectronics, or a related field, or equivalent relevant industry experience.
- Minimum 5 years of hands-on experience in analog or mixed-signal IC layout design.
- Strong understanding of CMOS layout principles, semiconductor process technologies, and layout-dependent effects.
- Proficiency with Cadence Virtuoso or Synopsys Custom Compiler.
- Experience with industry-standard physical verification tools and flows for DRC, LVS, DFM and parasitic extraction.
- Demonstrated experience with chip-level integration, floorplanning, I/O rings, power distribution, and hierarchical routing.
- Experience taking IC layouts through physical verification and tape-out
- Experience with advanced CMOS process technologies, including FD-SOI, high-voltage BCD and multi-layer interconnect structures.
- Strong ownership mentality.
- Effective team communication.
Helpful but not required:
- Experience with large-scale mixed-signal chip integration and complex power distribution networks.
- Experience with FinFET technologies.
- Experience with layout automation, scripting, or productivity tools such as SKILL, Tcl, or Python.